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/*
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* Copyright (c) 2018 Rockchip Electronics Co. Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef __RK817_CODEC_H__
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#define __RK817_CODEC_H__
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/* codec register */
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#define RK817_CODEC_BASE 0x0000
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#define RK817_CODEC_DTOP_VUCTL (RK817_CODEC_BASE + 0x12)
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#define RK817_CODEC_DTOP_VUCTIME (RK817_CODEC_BASE + 0x13)
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#define RK817_CODEC_DTOP_LPT_SRST (RK817_CODEC_BASE + 0x14)
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#define RK817_CODEC_DTOP_DIGEN_CLKE (RK817_CODEC_BASE + 0x15)
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#define RK817_CODEC_AREF_RTCFG0 (RK817_CODEC_BASE + 0x16)
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#define RK817_CODEC_AREF_RTCFG1 (RK817_CODEC_BASE + 0x17)
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#define RK817_CODEC_AADC_CFG0 (RK817_CODEC_BASE + 0x18)
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#define RK817_CODEC_AADC_CFG1 (RK817_CODEC_BASE + 0x19)
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#define RK817_CODEC_DADC_VOLL (RK817_CODEC_BASE + 0x1a)
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#define RK817_CODEC_DADC_VOLR (RK817_CODEC_BASE + 0x1b)
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#define RK817_CODEC_DADC_SR_ACL0 (RK817_CODEC_BASE + 0x1e)
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#define RK817_CODEC_DADC_ALC1 (RK817_CODEC_BASE + 0x1f)
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#define RK817_CODEC_DADC_ALC2 (RK817_CODEC_BASE + 0x20)
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#define RK817_CODEC_DADC_NG (RK817_CODEC_BASE + 0x21)
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#define RK817_CODEC_DADC_HPF (RK817_CODEC_BASE + 0x22)
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#define RK817_CODEC_DADC_RVOLL (RK817_CODEC_BASE + 0x23)
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#define RK817_CODEC_DADC_RVOLR (RK817_CODEC_BASE + 0x24)
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#define RK817_CODEC_AMIC_CFG0 (RK817_CODEC_BASE + 0x27)
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#define RK817_CODEC_AMIC_CFG1 (RK817_CODEC_BASE + 0x28)
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#define RK817_CODEC_DMIC_PGA_GAIN (RK817_CODEC_BASE + 0x29)
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#define RK817_CODEC_DMIC_LMT1 (RK817_CODEC_BASE + 0x2a)
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#define RK817_CODEC_DMIC_LMT2 (RK817_CODEC_BASE + 0x2b)
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#define RK817_CODEC_DMIC_NG1 (RK817_CODEC_BASE + 0x2c)
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#define RK817_CODEC_DMIC_NG2 (RK817_CODEC_BASE + 0x2d)
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#define RK817_CODEC_ADAC_CFG0 (RK817_CODEC_BASE + 0x2e)
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#define RK817_CODEC_ADAC_CFG1 (RK817_CODEC_BASE + 0x2f)
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#define RK817_CODEC_DDAC_POPD_DACST (RK817_CODEC_BASE + 0x30)
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#define RK817_CODEC_DDAC_VOLL (RK817_CODEC_BASE + 0x31)
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#define RK817_CODEC_DDAC_VOLR (RK817_CODEC_BASE + 0x32)
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#define RK817_CODEC_DDAC_SR_LMT0 (RK817_CODEC_BASE + 0x35)
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#define RK817_CODEC_DDAC_LMT1 (RK817_CODEC_BASE + 0x36)
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#define RK817_CODEC_DDAC_LMT2 (RK817_CODEC_BASE + 0x37)
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#define RK817_CODEC_DDAC_MUTE_MIXCTL (RK817_CODEC_BASE + 0x38)
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#define RK817_CODEC_DDAC_RVOLL (RK817_CODEC_BASE + 0x39)
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#define RK817_CODEC_DDAC_RVOLR (RK817_CODEC_BASE + 0x3a)
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#define RK817_CODEC_AHP_ANTI0 (RK817_CODEC_BASE + 0x3b)
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#define RK817_CODEC_AHP_ANTI1 (RK817_CODEC_BASE + 0x3c)
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#define RK817_CODEC_AHP_CFG0 (RK817_CODEC_BASE + 0x3d)
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#define RK817_CODEC_AHP_CFG1 (RK817_CODEC_BASE + 0x3e)
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#define RK817_CODEC_AHP_CP (RK817_CODEC_BASE + 0x3f)
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#define RK817_CODEC_ACLASSD_CFG1 (RK817_CODEC_BASE + 0x40)
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#define RK817_CODEC_ACLASSD_CFG2 (RK817_CODEC_BASE + 0x41)
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#define RK817_CODEC_APLL_CFG0 (RK817_CODEC_BASE + 0x42)
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#define RK817_CODEC_APLL_CFG1 (RK817_CODEC_BASE + 0x43)
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#define RK817_CODEC_APLL_CFG2 (RK817_CODEC_BASE + 0x44)
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#define RK817_CODEC_APLL_CFG3 (RK817_CODEC_BASE + 0x45)
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#define RK817_CODEC_APLL_CFG4 (RK817_CODEC_BASE + 0x46)
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#define RK817_CODEC_APLL_CFG5 (RK817_CODEC_BASE + 0x47)
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#define RK817_CODEC_DI2S_CKM (RK817_CODEC_BASE + 0x48)
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#define RK817_CODEC_DI2S_RSD (RK817_CODEC_BASE + 0x49)
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#define RK817_CODEC_DI2S_RXCR1 (RK817_CODEC_BASE + 0x4a)
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#define RK817_CODEC_DI2S_RXCR2 (RK817_CODEC_BASE + 0x4b)
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#define RK817_CODEC_DI2S_RXCMD_TSD (RK817_CODEC_BASE + 0x4c)
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#define RK817_CODEC_DI2S_TXCR1 (RK817_CODEC_BASE + 0x4d)
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#define RK817_CODEC_DI2S_TXCR2 (RK817_CODEC_BASE + 0x4e)
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#define RK817_CODEC_DI2S_TXCR3_TXCMD (RK817_CODEC_BASE + 0x4f)
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#define RK817_PMIC_CHIP_NAME (RK817_CODEC_BASE + 0xed)
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#define RK817_PMIC_CHIP_VER (RK817_CODEC_BASE + 0xee)
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/* RK817_CODEC_DTOP_DIGEN_CLKE */
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#define ADC_DIG_CLK_MASK (0xf << 4)
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#define ADC_DIG_CLK_SFT 4
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#define ADC_DIG_CLK_DIS (0x0 << 4)
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#define ADC_DIG_CLK_EN (0xf << 4)
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#define I2STX_CKE_EN (0x1 << 6)
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#define I2STX_CKE_DIS (0x0 << 6)
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#define DAC_DIG_CLK_MASK (0xf << 0)
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#define DAC_DIG_CLK_SFT 0
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#define DAC_DIG_CLK_DIS (0x0 << 0)
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#define DAC_DIG_CLK_EN (0xf << 0)
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/* RK817_CODEC_APLL_CFG5 */
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#define PLL_PW_DOWN (0x01 << 0)
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#define PLL_PW_UP (0x00 << 0)
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/* RK817_CODEC_DI2S_CKM */
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#define PDM_EN_MASK (0x1 << 3)
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#define PDM_EN_SFT 3
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#define PDM_EN_DISABLE (0x0 << 3)
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#define PDM_EN_ENABLE (0x1 << 3)
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#define SCK_EN_ENABLE (0x1 << 2)
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#define SCK_EN_DISABLE (0x0 << 2)
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#define RK817_I2S_MODE_MASK (0x1 << 0)
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#define RK817_I2S_MODE_SFT 0
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#define RK817_I2S_MODE_MST (0x1 << 0)
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#define RK817_I2S_MODE_SLV (0x0 << 0)
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/* RK817_CODEC_DDAC_SR_LMT0 */
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#define DACSRT_MASK (0x7 << 0)
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/* RK817_CODEC_DDAC_MUTE_MIXCTL */
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#define DACMT_ENABLE (0x1 << 0)
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#define DACMT_DISABLE (0x0 << 0)
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/* RK817_CODEC_DI2S_RXCR2 */
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#define VDW_RX_24BITS (0x17)
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#define VDW_RX_16BITS (0x0f)
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/* RK817_CODEC_DI2S_TXCR2 */
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#define VDW_TX_24BITS (0x17)
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#define VDW_TX_16BITS (0x0f)
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/* RK817_CODEC_AHP_CFG1 */
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#define HP_ANTIPOP_ENABLE (0x1 << 4)
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#define HP_ANTIPOP_DISABLE (0x0 << 4)
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/* RK817_CODEC_ADAC_CFG1 */
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#define PWD_DACBIAS_MASK (0x1 << 3)
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#define PWD_DACBIAS_SFT 3
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#define PWD_DACBIAS_DOWN (0x1 << 3)
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#define PWD_DACBIAS_ON (0x0 << 3)
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#define PWD_DACD_MASK (0x1 << 2)
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#define PWD_DACD_SFT 2
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#define PWD_DACD_DOWN (0x1 << 2)
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#define PWD_DACD_ON (0x0 << 2)
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#define PWD_DACL_MASK (0x1 << 1)
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#define PWD_DACL_SFT 1
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#define PWD_DACL_DOWN (0x1 << 1)
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#define PWD_DACL_ON (0x0 << 1)
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#define PWD_DACR_MASK (0x1 << 0)
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#define PWD_DACR_SFT 0
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#define PWD_DACR_DOWN (0x1 << 0)
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#define PWD_DACR_ON (0x0 << 0)
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/* RK817_CODEC_AADC_CFG0 */
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#define ADC_L_PWD_MASK (0x1 << 7)
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#define ADC_L_PWD_SFT 7
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#define ADC_L_PWD_DIS (0x0 << 7)
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#define ADC_L_PWD_EN (0x1 << 7)
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#define ADC_R_PWD_MASK (0x1 << 6)
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#define ADC_R_PWD_SFT 6
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#define ADC_R_PWD_DIS (0x0 << 6)
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#define ADC_R_PWD_EN (0x1 << 6)
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/* RK817_CODEC_AMIC_CFG0 */
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#define MIC_DIFF_MASK (0x1 << 7)
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#define MIC_DIFF_SFT 7
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#define MIC_DIFF_DIS (0x0 << 7)
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#define MIC_DIFF_EN (0x1 << 7)
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#define PWD_PGA_L_MASK (0x1 << 5)
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#define PWD_PGA_L_SFT 5
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#define PWD_PGA_L_DIS (0x0 << 5)
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#define PWD_PGA_L_EN (0x1 << 5)
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#define PWD_PGA_R_MASK (0x1 << 4)
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#define PWD_PGA_R_SFT 4
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#define PWD_PGA_R_DIS (0x0 << 4)
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#define PWD_PGA_R_EN (0x1 << 4)
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enum {
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RK817_HIFI,
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RK817_VOICE,
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};
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enum {
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RK817_MONO = 1,
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RK817_STEREO,
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};
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enum {
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OFF,
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RCV,
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SPK_PATH,
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HP_PATH,
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HP_NO_MIC,
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BT,
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SPK_HP,
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RING_SPK,
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RING_HP,
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RING_HP_NO_MIC,
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RING_SPK_HP,
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};
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enum {
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MIC_OFF,
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MAIN_MIC,
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HANDS_FREE_MIC,
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BT_SCO_MIC,
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};
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struct rk817_reg_val_typ {
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unsigned int reg;
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unsigned int value;
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};
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struct rk817_init_bit_typ {
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unsigned int reg;
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unsigned int power_bit;
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unsigned int init_bit;
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};
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#endif /* __RK817_CODEC_H__ */
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